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may 2010 doc id 17399 rev 1 1/11 AN3202 application note how to configure the spear600 general purpose timers (gpts) introduction this application note provides information about how to configure the general purpose timers (gpts) integrated in th e spear600 embedded mpu family. general purpose timers (gpts) play an important role in any system as they provide a means of calculating time for controlling the ex ecution of various oper ations. in case of an operating system, they are used for the system tick generation, usually every 10 ms; in other applications they can be used to get a finer gr anularity for controlling the timing of events. the purpose of this application note is to explain how to read the free running timer counter and configure the clock source of the various gpts that are integrated in the spear600 architecture. www.st.com
contents AN3202 2/11 doc id 17399 rev 1 contents 1 general purpose timers (gpts) in spear600 . . . . . . . . . . . . . . . . . . . . . 3 2 reading a free-running timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 scenario with slow cnt_clk and fast read_clk . . . . . . . . . . . . . . . . . 7 4 how to configure cnt_clk and read_clk to be sync hronous . . . . . . 8 5 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
AN3202 general purpose ti mers (gpts) in spear600 doc id 17399 rev 1 3/11 1 general purpose timers (gpts) in spear600 in the spear600 architecture, th ere are five different gpt bl ocks located in the various subsystems. each timer block consists of two independent channels, each one with a 16-bit counter register. table 1. gpts in spear600 each timer has a read_clk , input which is the apb clock (pclk), and a cnt_clk , which can be selected by the user from a list of clock sources. read_clk (pclk): when spear600 is in normal mode, it takes the input from pll1 divided by a programmable prescaler, whose reset values impose the ratio 1:2:4 to the core_clk, hclk and pclk clocks. when spear600 is in slow mode, it takes directly the input from the osci signal. cnt_clk : the clock source can be selected as either a fixed 48 mhz or the pll1 itself divided by a programmable prescaler, which is defined in the prsc1_clk_cfg register (0xfca8_0044) for gpt1/gpt2/gpt3, prsc2_clk_cfg register (0xfca8_0048) for gpt4 and prsc3_clk_cfg register (0xfca8_004c) for gpt5. the cnt_clk may then be further divided by a gpt internal 4-bit prescaler able to divide up to 256 times (?/256?). figure 1. gpt clock sources the following table describes the clock selectors (clock_sel) for each gpt. subsystem base address gpt1 arm1 0xf000_0000 gpt2 arm2 0xf000_0000 gpt3 basic 0xfc80_0000 gpt4 application 1 0xd800_0000 gpt5 application 2 0xd808_0000 gp t ch1 gpt ch2 read_clk (p clk ) cnt_clk pll3 (48mhz) prscx_clk_cfg pll1 (332mhz)/ osci (24mhz) hclk/pclk prescaler mux pll1 (332mhz) clock_sel int_ p rsc
general purpose timers (gpts) in spear600 AN3202 4/11 doc id 17399 rev 1 the spear600 gpts always generate precise alarm interrupts, for example in the case of a system tick for a rtos. nevertheless, as you can see in section 2: reading a free-running timer counter , gpts can return unpredictable read values when they are running and the input clock is asynchronous (or not in phase). table 2. gptx clock source selector register address value gpt1 prph_clk_cfg [08] 0xfca8_0028 (bit8) 0: pll3 48 mhz 1: pll1 ( prsc1_clk_cfg ) gpt2 prph_clk_cfg[09] 0xfca8_0028 (bit9) 0: pll3 48 mhz 1: pll1 ( prsc1_clk_cfg ) gpt3 prph_clk_cfg[10] 0xfca8_0028 (bit10) 0: pll3 48 mhz 1: pll1 ( prsc1_clk_cfg ) gpt4 prph_clk_cfg[11] 0xfca8_0028 (bit11) 0: pll3 48 mhz 1: pll1 ( prsc2_clk_cfg ) gpt5 prph_clk_cfg[12] 0xfca8_0028 (bit12) 0: pll3 48 mhz 1: pll1 ( prsc3_clk_cfg )
AN3202 reading a free-running timer counter doc id 17399 rev 1 5/11 2 reading a free-running timer counter when the gpt interrupt is enabled, the interrupts generated at each timer wrap-around condition are always triggered at the right frequency, however reading the timer counter when the timer itself is active and free-ru nning may present some difficulties which are described below. in a simplified scenario, a hardware timer block can be seen just as a simple counter register with two input clocks: cnt_clk for incrementing/decrementing the counter and read_clk for synchronizing the read accesses of the bus the timer is connected to. figure 2. simplified timer the two clocks can be either synchronous, coming from the same source pclk, or completely asynchronous, for example coming from two different sources. when the two clocks involved in the scenario are asynchronous, then the value retrieved by the cpu in a read counter operation is unpredictable, and might be completely different from the real value in the register. the situation is due to the fact that the read_clk is sampling the counter bits while they are in a transitioning, unstable phase. figure 3. sampling a counter bit in an unstable state the above scenario may take place during any kind of transition (0->1 or 1->0) and for any bit in the register. if one of the bits impacted has a large weight (significant position) in the counter, then the difference between the value returned in the read transaction and the real value of the counter can be very large. cnt_clk 0 0 1 0 1 ? read_clk cnt_clk read_clk bit_n t0 t1 t2 t0: on cnt_clk rising edge, bit_n start a 0->1 transitioning t1: on read_c lk rising edge, bit_n is sampled in an unstable state t2: bit_n reaches a stable state
reading a free-running timer counter AN3202 6/11 doc id 17399 rev 1 let?s take as an example a counting down 16-bit counter transitioning from the value 1000_0000_0000_0000 (0x8000) to 0111_1111_1111_1111 (0x7fff). since the transition time of the 16 bits can be slightly different between each other, then the 16-bit counter value could be read by the cpu randomly as 0x0000 or 0xffff leading to a big difference from its real value. a similar scenario may also occur in case the two clocks are synchronous, but not in phase. in this case, in fact, the read_clk may sample the bit during its unstable state period. so, the two clocks must be synchronous and in phase.
AN3202 scenario with slow cnt_clk and fast read_clk doc id 17399 rev 1 7/11 3 scenario with slow cnt_clk and fast read_clk in certain cases, for example when the timer is used by an operating system to generate the system tick, the cnt_clk (after prescaling) is usually much slower than read_clk . for example, let?s suppose you need to generate a tick every 10 ms; the gpt with a clock source of 48 mhz might be programmed using a ?/32? internal prescaler and a counter equal to 15000. this results in a great number (around 60) read_clk ? sampling cycles ? for every single cnt_clk cycle. or, in other words, cnt_clk is about 60 times slower than read_clk . figure 4. cnt_clk at low frequency let?s see what happens if the cpu does three consecutive read operations instead of a single one. since the bit inst ability lasts much less than the cnt_clk time period, we can say that, out of 3 read_clk edges, only one will ever fall in to the bit instability window. the other two are stable. moreover, since cnt_clk is about 60 times slower than read_clk, the two stable read operations return counter values that differ by 1 in the worst case, which is when there is a cnt_clk rising edge between the first and third read operations. of course, interrupts should be disabled during the reads. so, reading three times the counter and discharging the unstable value (if any) is a valid workaround that can be used for all gpts of spear600 in similar scenarios. in particular, this method might be used for gpt1 , gpt2 and gpt3 . in general, this workaround is valid when the minimum period of cnt_clk is greater than 3 times the read_cycle_time. the read_cycle_time depends on the cpu frequency , and also on the way the reads are implemented, so they should be carefully evaluate d . read_clk ( p c lk == 83 mhz ) cnt_clk (48mhz/32 == 1.5 mhz) bit_n t0 t1 t2 t0: bit_n is sampled in an unstable state t1 & t2: bit_n is sampled in a stable state. samples are assumed to happen every 3 read_clk cycles.
how to configure cnt_clk and read_clk to be synchronous AN3202 8/11 doc id 17399 rev 1 4 how to configure cnt_clk and read_clk to be synchronous this method, which is very simp le to implement, is nevertheless guaranteed to work for gpt4 and gpt5 only. the most common conf iguration is when spear600 is in normal mode with system clocks fed by pll1. in case the system is set in this mode, you can ju st select pll1 as cnt_clk to guarantee the synchronicity between cnt_clk and read_clk. to set the input clock source of gptx to pll1 you need to use prph_clk_cfg register (0xfca8_0028). there are five different bits, one for each gpt block. for gpt4 : prph_clk_cfg [11] = 1 for gpt5 : prph_clk_cfg [12] = 1 in case spear600 enters the slow mode, for example to save power after detecting a period of inactivity, the hclk/pclk system clocks are directly fed from the osci at 30 mhz. in this mode read_clk (osci) and cnt_clk (pll1) become asynchronous again.
AN3202 summary doc id 17399 rev 1 9/11 5 summary a general purpose timer can be seen as a simple counter with two clocks in input: read_clk (for the slave interface) and cnt_clk (for incrementing/decrementing the counter). the cnt_clk for the gpt in spear600 can be selected between a fixed 48 mhz source and pll1, which is also the source clock for the rest of the system. the read_clk is derived from pll1 in normal mode (pclk) and from the 30 mhz osci in slow mode. having a fixed clock source different from the system clock has the advantage of eliminating the need for reconfiguring the gpt registers if the system clock frequency is slowed down. however, it introduces the possibility of obtaining an unpredictable result when reading the timer value, due to the non-synchronous operation of the two clocks. in case cnt_clk is much slower than read_clk, three consecutives read of the counter (3- reads workaround) guarantees to have at least two stable values with a maximum difference of 1. the following table summarizes the suggested solutions for this issue: table 3. summary of the solutions subsystem solution in normal mode solution in slow mode gpt1 arm1 3-reads workaround 3-reads workaround gpt2 arm2 3-reads workaround 3-reads workaround gpt3 basic 3-reads workaround 3-reads workaround gpt4 application1 keep read_clk and cnt_clk synchronous 3-reads workaround gpt5 application2 keep read_clk and cnt_clk synchronous 3-reads workaround
revision history AN3202 10/11 doc id 17399 rev 1 6 revision history table 4. document revision history date revision changes 03-may-2010 1 initial release.
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